Redundancy Yield Model for SRAMS

نویسنده

  • Nermine H. Ramadan
چکیده

This paper describes a model developed to calculate the number of redundant good die per wafer. A block redundancy scheme is used here, where the entire defective memory subarray is replaced by a redundant element. A formula is derived to calculate the amount of improvement expected after redundancy. This improvement is given in terms of the ratio of the overall good die per wafer to the original good die per wafer after considering some key factors. These factors are memory area, available redundant elements, defect density and defect types with respect to the total reject die and defect distribution on the memory area. The model uses Poisson’s equation to define the yield, then the appropriate boundary conditions that account for those factors are applied. In the case of a new product, knowing the die size, memory design, and total die per wafer, the model can be used to predict the redundancy yield for this product at different initial yield values. Optimizing the memory design by varying the number of memory blocks and/or redundant elements to enhance redundancy is also discussed. The model was applied to three products from two different process generations and showed good agreement with the measured data. Introduction Due to the continuing increase in the size of memory arrays, reaching a high yield from the same wafer is more challenging than ever. Redundancy is a way to improve the wafer yield and to reduce the test cost per good die by fixing potentially repairable defects. In order to forecast the volume of a certain product when redundancy is applied, it is important to estimate, as accurately as possible, the number of die gained after redundancy. Redundancy is the process of replacing defective circuitry with spare elements. In SRAMs, rows and/or columns can be replaced, as well as an entire subarray. In a previous study[1], a redundant yield estimation methodology was developed. It is applicable to row, column or block redundancy schemes. It distinguishes between repairable and non-repairable faults within a memory block. In order to apply this method, new CAD tools are required. This method is useful if row or column redundancy is used. This paper will focus only on the yield estimation for block redundancy, as block redundancy was preferred over row and column redundancy for the SRAM architecture. It is usually easier to replace the entire subarray. This might seem like overkill; however, replacing the entire subarray allows for the replacement of defective peripheral circuits in addition to just the memory array elements. It also allows for the replacement of multiple bad bits, or other combinations of failing bits, rows and columns. A yield multiplier M is defined as the ratio of the total good die after redundancy to the original good die per wafer, or M = total redundant good/original good (1) so that the redundant yield , Yred , is given as Yred = M x Y (2) where Y is the initial yield. Forecasting of the redundancy yields is based on how accurately the factor M is calculated. A formula for M was obtained by using the correlated defect model. According to this model, an expression for the yield of die containing a number of defects, I, is given by yI={(n+I+1)! x (DA) }/{(I! n )x(1+D A/n)} x f (3) where yI = yield of a die with I defects Intel Technology Journal Q4’97 2 D = average defect density ( #/cm ) A = die area (cm ) n= correlation factor between defects f = fraction of the die area that contains the defects The yield of die with zero defects can be obtained by setting I = 0 and f = 1 as Y = 1 / { 1 + (A D / n) } (4) With n = 4 and using equation (4) to substitute for the defect density, equation (3) becomes yI= Y x ((I+3)(I+2)(I+1) /6) x f I x ( 1-Y ) I (5) Introducing g as the fraction of repairable defects, g varies depending on the number of repaired defects. An expression for M was obtained by summing yI over the ratio of correctable defects and substituting in (2) M = 1 + ΣI = 1 ((I+3)(I+2)(I+1) /6) x( g f ( 1-Y )) I (6) M was calculated by entering arbitrary values of g and f in equation (6). However, there was no evidence to support the values of the repairable defect density represented by g used to calculate M. Another formula was used to estimate the yield multiplier M . The yield is derived from Poisson’s equation [2]

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Reducing Test Time of Embedded SRAMs

Compared with traditional functional fault models, fault model obtained from an Inductive Fault Analysis (IFA) test flow can provide an attractive basis for obtaining a good estimate of the overall test quality in terms of defect level and yield. However, the associated surging test time due to increased SRAM capacity is becoming a major challenge when testing either standalone or embedded SRAM...

متن کامل

Yield Analysis of Compiler-Based Arrays of Embedded SRAMs

This paper presents a detailed analysis of the yield of embedded static random access memories (eSRAM) which are generated using a compiler. Defect and fault analysis inclusive of industrial data are presented for these chips by taking into accotmt the design constructs (referred to as kernels) and the physical properties of the layout. The new tool CAYA (Compiler-based Array Yield Analysis) is...

متن کامل

Yield-Aware Leakage Power Reduction of On-Chip SRAMs

Yield-Aware Leakage Power Reduction of On-Chip SRAMs Afshin Nourivand, Ph.D. Concordia University, 2010 Leakage power dissipation of on-chip static random access memories (SRAMs) constitutes a significant fraction of the total chip power consumption in state-ofthe-art microprocessors and system-on-chips (SoCs). Scaling the supply voltage of SRAMs during idle periods is a simple yet effective te...

متن کامل

An Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy

Built-in self-test (BIST) refers to those testing techniques where additional hardware is added to a design so that testing is accomplished without the aid of external hardware. Usually, a pseudo-random generator is used to apply test vectors to the circuit under test and a data compactor is used to produce a signature. To increase the reliability and yield of embedded memories, many redundancy...

متن کامل

Efficient Built-in Self-repair Strategy for Embedded Sram with Selectable Redundancy

Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy for embedded memories. This paper proposes an efficient BISR strategy which consists of a Built-In Self-Test (BIST) module, a Built-In Address-Analysis (BIAA) module and a Multiplexer (MUX) module. The BISR is designed flexible that it can provide four operation modes to SRAM users. Each fault address can be ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1997